1. Field of the Invention
The present invention relates to an image processor for forming a visible image based on digitized video signal through interlaced scanning according to a National Television Standard Committee (NTSC) format for constructing one frame with even field and odd field.
2. Description of the Prior Art
To display a picture or an image on a TV screen, a video signal is subjected to interlaced scanning. Data of one frame worth of video signal is divided into data for odd number scan lines (i.e., for the odd field as represented by the dotted lines in FIG. 2) and even number scan lines (i.e., for the even field as represented by the solid lines in FIG. 2).
Generally, the video signal includes data for scanning 525 vertically aligned horizontal lines using interlaced scanning. About 480 seen lines actually appear on the monitor screen, The remaining 45 lines do not appear on the monitor screen and non-display periods for this 45 lines is termed flyback. Therefore, about 480 lines worth of information are required to digitize end store one complete picture.
A picture can be formed by using the same field information when scanning both the odd field and the even field. For example, odd field information can be used during scanning for both even and odd fields. By doing so, capacity of external memory units required for storing digitized video information can be reduced. However, this generates flicker in the vertical direction. An image processor shown in FIG. 1 has been proposed to prevent the occurrence of flicker. With the configuration shown in FIG. 1, 240 lines of display information are artificially increased to 480 lines of information during reproduction.
The image processor shown in FIG. 1 includes a central processing unit (CPU) 32, a field memory 21, a synchronization signal generator 28, three color blocks 26a through 26c, an RGB encoder 27, and a television monitor 30. Each of the red component block 26a, the green component block 26b and the blue component block 26c includes a line memory 22, a calculation circuit 23, a selector 24 and a digital-to-analog (D/A) converter 25.
The field memory 21 is connected to receive output from an external memory unit 20 under the aegis of the CPU 32. The field memory 21 is further connected to receive a vertical synchronization signal 33 and a horizontal synchronization signal 34 from the synchronization signal generator 28. Output of the field memory 21 is connected separately to the line memory 22, the calculation circuit 23 and the selector 24 of each of the color blocks 26a through 26c.
The line memory 22 of each of the color blocks 26a through 26c is additionally connected to receive the horizontal synchronization signal 34 from the synchronization signal generator 28. Each calculation circuit 23 is connected to receive outputs from its associated line memory 22 and the field memory 21. Each selector 24 is connected to receive outputs from its associated calculation circuit 23 and the field memory 21. A field identification signal 29 is applied to the respective selectors 24 from the synchronization signal generator 28. Each digital-to-analog converter 25 is connected to receive output from its associated selector 24. The output of each D/A converter 25 is applied to the RGB encoder 27, which is also connected to receive output from the synchronization signal generator 28. The output from the RGB encoder 27 is connected to the television monitor 30.
In operation, the external memory unit 20 stores digitized video signal relating to only odd field information. The CPU 32 retrieves such a video signal from the external memory unit 20 and writes it in the field memory 21. Red (R) component contained in the video signal is retrieved from the field memory 21 in timed relation to the vertical synchronization signal 33 and the horizontal Synchronization signal supplied from the synchronization signal generator 28 and is written in the line memory 22 and the calculation circuit 23, both shown in block 26a.
The calculation circuit 23 also receives information outputted from the line memory 22. The information outputted from the line memory 22 is the preceding line information with respect to the line information currently supplied to the calculation circuit 23 from the field memory 21. Therefore, the calculation circuit 23 is supplied with two pieces of scan line information for vertically adjacent lines of the odd field. Based on the two pieces of scan line information thus supplied to the calculation circuit 23, the circuit 23 calculates and produces image information to be used for scanning the even field line between these two vertically adjacent odd field lines. Stated differently, the calculation circuit 23 produces quasi-information for the even field lines based on the odd field line information.
The even field lane information produced in this way is supplied to the selector 24 along with the odd field line information retrieved from the field memory 21. One or the other is selectively outputted from the selector 24 to the associated D/A converter 25 according to a field identification signal 29 outputted from the synchronization signal generator 28. If the field identification signal 29 indicates the odd field, the odd field line information supplied from the field memory 21 is selected by the selector 24 and outputted to the associated D/A converter 25. On the other hand, if the field identification signal 29 indicates the even field, the results of the calculation performed in the calculation circuit 23 are selected by the selector 24 and outputted to the D/A converter 25.
The output from the selector 24 is subjected to digital-to-analog conversion in the D/A converter 25 and the resultant analog signal is sent to the RGB encoder 27. In the same manner, the green (G) and blue (B) components which form the remainder of the video signal are retrieved from the field memory 21 and processed in the green component block 26b and the blue component block 26c, respectively, in the same manner that the red component is processed in the red component block 26a. The resultant signals are converted into analog signals and set to the RGB encoder
The red (R), green (G) and blue (B) analog signals inputted into the RGB encoder 27 are converted into an NTSC video signal 31 for forming an image on the television monitor 30.
Because only odd field information is stored in the field memory 21, an image processor with the configuration shown in FIG. 1 can operate with the field memory 21 having only half the normally required memory capacity. However, there has been known problem in that additional components, such as the line memory 22, are required in each block 26a, 26b and 26c for interpolating the red, green and blue color components that make up the image. The extra components complicate the structure of the device and increase production costs.